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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\lab\lab1\impl\gwsynthesis\lab1.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>D:\lab\lab1\src\lab1.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.11.01 Education (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2AR-LV18QN88C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2AR-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Jun 19 21:21:19 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.95V 85C C8/I7</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.05V 0C C8/I7</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>53</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>52</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">NO.</th>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>1</td>
<td>Clock</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>Clock_ibuf/I </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>Clock</td>
<td>100.000(MHz)</td>
<td>315.706(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>Clock</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>Clock</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>6.832</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_flag_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.133</td>
</tr>
<tr>
<td>2</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_23_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>3</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_1_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>4</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_2_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>5</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_3_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>6</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_4_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>7</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_5_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>8</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_6_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>9</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_7_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>10</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_8_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>11</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_9_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>12</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_10_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>13</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_11_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>14</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_18_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>15</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_19_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>16</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_20_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>17</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_21_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>18</td>
<td>7.259</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_22_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.706</td>
</tr>
<tr>
<td>19</td>
<td>7.283</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_12_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.682</td>
</tr>
<tr>
<td>20</td>
<td>7.283</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_13_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.682</td>
</tr>
<tr>
<td>21</td>
<td>7.283</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_14_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.682</td>
</tr>
<tr>
<td>22</td>
<td>7.283</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_15_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.682</td>
</tr>
<tr>
<td>23</td>
<td>7.283</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_16_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.682</td>
</tr>
<tr>
<td>24</td>
<td>7.283</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_17_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.682</td>
</tr>
<tr>
<td>25</td>
<td>7.295</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_0_s0/RESET</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.670</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.318</td>
<td>count_value_flag_s0/Q</td>
<td>IO_voltage_reg_s1/CE</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.329</td>
</tr>
<tr>
<td>2</td>
<td>0.424</td>
<td>count_value_reg_2_s0/Q</td>
<td>count_value_reg_2_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.435</td>
</tr>
<tr>
<td>3</td>
<td>0.425</td>
<td>IO_voltage_reg_s1/Q</td>
<td>IO_voltage_reg_s1/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.436</td>
</tr>
<tr>
<td>4</td>
<td>0.425</td>
<td>count_value_reg_6_s0/Q</td>
<td>count_value_reg_6_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.436</td>
</tr>
<tr>
<td>5</td>
<td>0.425</td>
<td>count_value_reg_8_s0/Q</td>
<td>count_value_reg_8_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.436</td>
</tr>
<tr>
<td>6</td>
<td>0.425</td>
<td>count_value_reg_12_s0/Q</td>
<td>count_value_reg_12_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.436</td>
</tr>
<tr>
<td>7</td>
<td>0.425</td>
<td>count_value_reg_14_s0/Q</td>
<td>count_value_reg_14_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.436</td>
</tr>
<tr>
<td>8</td>
<td>0.425</td>
<td>count_value_reg_18_s0/Q</td>
<td>count_value_reg_18_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.436</td>
</tr>
<tr>
<td>9</td>
<td>0.425</td>
<td>count_value_reg_20_s0/Q</td>
<td>count_value_reg_20_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.436</td>
</tr>
<tr>
<td>10</td>
<td>0.483</td>
<td>count_value_reg_0_s0/Q</td>
<td>count_value_reg_0_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.494</td>
</tr>
<tr>
<td>11</td>
<td>0.539</td>
<td>count_value_reg_3_s0/Q</td>
<td>count_value_reg_3_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.550</td>
</tr>
<tr>
<td>12</td>
<td>0.539</td>
<td>count_value_reg_4_s0/Q</td>
<td>count_value_reg_4_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.550</td>
</tr>
<tr>
<td>13</td>
<td>0.542</td>
<td>count_value_reg_17_s0/Q</td>
<td>count_value_reg_17_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.553</td>
</tr>
<tr>
<td>14</td>
<td>0.546</td>
<td>count_value_reg_9_s0/Q</td>
<td>count_value_reg_9_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.557</td>
</tr>
<tr>
<td>15</td>
<td>0.546</td>
<td>count_value_reg_10_s0/Q</td>
<td>count_value_reg_10_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.557</td>
</tr>
<tr>
<td>16</td>
<td>0.546</td>
<td>count_value_reg_11_s0/Q</td>
<td>count_value_reg_11_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.557</td>
</tr>
<tr>
<td>17</td>
<td>0.546</td>
<td>count_value_reg_15_s0/Q</td>
<td>count_value_reg_15_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.557</td>
</tr>
<tr>
<td>18</td>
<td>0.546</td>
<td>count_value_reg_16_s0/Q</td>
<td>count_value_reg_16_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.557</td>
</tr>
<tr>
<td>19</td>
<td>0.546</td>
<td>count_value_reg_21_s0/Q</td>
<td>count_value_reg_21_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.557</td>
</tr>
<tr>
<td>20</td>
<td>0.547</td>
<td>count_value_reg_5_s0/Q</td>
<td>count_value_reg_5_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.558</td>
</tr>
<tr>
<td>21</td>
<td>0.547</td>
<td>count_value_reg_7_s0/Q</td>
<td>count_value_reg_7_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.558</td>
</tr>
<tr>
<td>22</td>
<td>0.547</td>
<td>count_value_reg_19_s0/Q</td>
<td>count_value_reg_19_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.558</td>
</tr>
<tr>
<td>23</td>
<td>0.549</td>
<td>count_value_reg_23_s0/Q</td>
<td>count_value_reg_23_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.560</td>
</tr>
<tr>
<td>24</td>
<td>0.552</td>
<td>count_value_reg_22_s0/Q</td>
<td>count_value_reg_22_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.563</td>
</tr>
<tr>
<td>25</td>
<td>0.556</td>
<td>count_value_reg_1_s0/Q</td>
<td>count_value_reg_1_s0/D</td>
<td>Clock:[R]</td>
<td>Clock:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.567</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>0.972</td>
<td>1.972</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>Clock</td>
<td>count_value_reg_22_s0</td>
</tr>
<tr>
<td>2</td>
<td>0.972</td>
<td>1.972</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>Clock</td>
<td>count_value_reg_21_s0</td>
</tr>
<tr>
<td>3</td>
<td>0.972</td>
<td>1.972</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>Clock</td>
<td>count_value_reg_19_s0</td>
</tr>
<tr>
<td>4</td>
<td>0.972</td>
<td>1.972</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>Clock</td>
<td>count_value_reg_15_s0</td>
</tr>
<tr>
<td>5</td>
<td>0.972</td>
<td>1.972</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>Clock</td>
<td>count_value_reg_7_s0</td>
</tr>
<tr>
<td>6</td>
<td>0.972</td>
<td>1.972</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>Clock</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td>7</td>
<td>0.972</td>
<td>1.972</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>Clock</td>
<td>count_value_reg_16_s0</td>
</tr>
<tr>
<td>8</td>
<td>0.972</td>
<td>1.972</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>Clock</td>
<td>count_value_reg_9_s0</td>
</tr>
<tr>
<td>9</td>
<td>0.972</td>
<td>1.972</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>Clock</td>
<td>count_value_reg_10_s0</td>
</tr>
<tr>
<td>10</td>
<td>0.972</td>
<td>1.972</td>
<td>1.000</td>
<td>High Pulse Width</td>
<td>Clock</td>
<td>IO_voltage_reg_s1</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.832</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.604</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_flag_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.798</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.604</td>
<td>0.806</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C27[1][A]</td>
<td style=" font-weight:bold;">count_value_flag_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][A]</td>
<td>count_value_flag_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C27[1][A]</td>
<td>count_value_flag_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.593, 50.854%; route: 1.308, 41.740%; tC2Q: 0.232, 7.406%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_23_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[2][B]</td>
<td style=" font-weight:bold;">count_value_reg_23_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[2][B]</td>
<td>count_value_reg_23_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C29[2][B]</td>
<td>count_value_reg_23_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[0][B]</td>
<td style=" font-weight:bold;">count_value_reg_1_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[0][B]</td>
<td>count_value_reg_1_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C26[0][B]</td>
<td>count_value_reg_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_2_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[1][A]</td>
<td>count_value_reg_2_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C26[1][A]</td>
<td>count_value_reg_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[1][B]</td>
<td style=" font-weight:bold;">count_value_reg_3_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[1][B]</td>
<td>count_value_reg_3_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C26[1][B]</td>
<td>count_value_reg_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_4_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[2][A]</td>
<td>count_value_reg_4_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C26[2][A]</td>
<td>count_value_reg_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[2][B]</td>
<td style=" font-weight:bold;">count_value_reg_5_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[2][B]</td>
<td>count_value_reg_5_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C26[2][B]</td>
<td>count_value_reg_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[0][A]</td>
<td style=" font-weight:bold;">count_value_reg_6_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[0][A]</td>
<td>count_value_reg_6_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C27[0][A]</td>
<td>count_value_reg_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[0][B]</td>
<td style=" font-weight:bold;">count_value_reg_7_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[0][B]</td>
<td>count_value_reg_7_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C27[0][B]</td>
<td>count_value_reg_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][B]</td>
<td style=" font-weight:bold;">count_value_reg_9_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][B]</td>
<td>count_value_reg_9_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C27[1][B]</td>
<td>count_value_reg_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_10_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[2][A]</td>
<td>count_value_reg_10_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C27[2][A]</td>
<td>count_value_reg_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[2][B]</td>
<td style=" font-weight:bold;">count_value_reg_11_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[2][B]</td>
<td>count_value_reg_11_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C27[2][B]</td>
<td>count_value_reg_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[0][A]</td>
<td style=" font-weight:bold;">count_value_reg_18_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[0][A]</td>
<td>count_value_reg_18_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C29[0][A]</td>
<td>count_value_reg_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_19_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[0][B]</td>
<td style=" font-weight:bold;">count_value_reg_19_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[0][B]</td>
<td>count_value_reg_19_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C29[0][B]</td>
<td>count_value_reg_19_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_20_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[1][A]</td>
<td>count_value_reg_20_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C29[1][A]</td>
<td>count_value_reg_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[1][B]</td>
<td style=" font-weight:bold;">count_value_reg_21_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[1][B]</td>
<td>count_value_reg_21_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C29[1][B]</td>
<td>count_value_reg_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.177</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_22_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.177</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_22_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[2][A]</td>
<td>count_value_reg_22_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C29[2][A]</td>
<td>count_value_reg_22_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.211%; route: 0.872, 32.214%; tC2Q: 0.232, 8.575%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.283</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.153</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.153</td>
<td>0.346</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[0][A]</td>
<td style=" font-weight:bold;">count_value_reg_12_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[0][A]</td>
<td>count_value_reg_12_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C28[0][A]</td>
<td>count_value_reg_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.738%; route: 0.848, 31.611%; tC2Q: 0.232, 8.651%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.283</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.153</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.153</td>
<td>0.346</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[0][B]</td>
<td style=" font-weight:bold;">count_value_reg_13_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[0][B]</td>
<td>count_value_reg_13_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C28[0][B]</td>
<td>count_value_reg_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.738%; route: 0.848, 31.611%; tC2Q: 0.232, 8.651%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.283</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.153</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.153</td>
<td>0.346</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_14_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[1][A]</td>
<td>count_value_reg_14_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C28[1][A]</td>
<td>count_value_reg_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.738%; route: 0.848, 31.611%; tC2Q: 0.232, 8.651%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.283</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.153</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.153</td>
<td>0.346</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[1][B]</td>
<td style=" font-weight:bold;">count_value_reg_15_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[1][B]</td>
<td>count_value_reg_15_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C28[1][B]</td>
<td>count_value_reg_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.738%; route: 0.848, 31.611%; tC2Q: 0.232, 8.651%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.283</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.153</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.153</td>
<td>0.346</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_16_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[2][A]</td>
<td>count_value_reg_16_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C28[2][A]</td>
<td>count_value_reg_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.738%; route: 0.848, 31.611%; tC2Q: 0.232, 8.651%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.283</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.153</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.153</td>
<td>0.346</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[2][B]</td>
<td style=" font-weight:bold;">count_value_reg_17_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[2][B]</td>
<td>count_value_reg_17_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C28[2][B]</td>
<td>count_value_reg_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 59.738%; route: 0.848, 31.611%; tC2Q: 0.232, 8.651%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.295</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.141</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>17.436</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>7.703</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>7.860</td>
<td>0.156</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td>n55_s5/I2</td>
</tr>
<tr>
<td>8.430</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R26C27[3][A]</td>
<td style=" background: #97FFFF;">n55_s5/F</td>
</tr>
<tr>
<td>8.602</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td>n55_s2/I0</td>
</tr>
<tr>
<td>9.172</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R26C28[3][A]</td>
<td style=" background: #97FFFF;">n55_s2/F</td>
</tr>
<tr>
<td>9.345</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C28[0][B]</td>
<td>n55_s1/I1</td>
</tr>
<tr>
<td>9.807</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R27C28[0][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>10.141</td>
<td>0.335</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_0_s0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>14.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>17.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[2][A]</td>
<td>count_value_reg_0_s0/CLK</td>
</tr>
<tr>
<td>17.436</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C28[2][A]</td>
<td>count_value_reg_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.602, 60.001%; route: 0.836, 31.310%; tC2Q: 0.232, 8.689%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 4.230, 56.616%; route: 3.241, 43.384%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.318</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.647</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_flag_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>IO_voltage_reg_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][A]</td>
<td>count_value_flag_s0/CLK</td>
</tr>
<tr>
<td>5.519</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][A]</td>
<td style=" font-weight:bold;">count_value_flag_s0/Q</td>
</tr>
<tr>
<td>5.647</td>
<td>0.127</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td style=" font-weight:bold;">IO_voltage_reg_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td>IO_voltage_reg_s1/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C27[0][A]</td>
<td>IO_voltage_reg_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.127, 38.638%; tC2Q: 0.202, 61.362%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.424</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.753</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[1][A]</td>
<td>count_value_reg_2_s0/CLK</td>
</tr>
<tr>
<td>5.519</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R26C26[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_2_s0/Q</td>
</tr>
<tr>
<td>5.521</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R26C26[1][A]</td>
<td>n28_s/I1</td>
</tr>
<tr>
<td>5.753</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R26C26[1][A]</td>
<td style=" background: #97FFFF;">n28_s/SUM</td>
</tr>
<tr>
<td>5.753</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C26[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[1][A]</td>
<td>count_value_reg_2_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C26[1][A]</td>
<td>count_value_reg_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.306%; route: 0.001, 0.281%; tC2Q: 0.202, 46.413%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.754</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>IO_voltage_reg_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>IO_voltage_reg_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td>IO_voltage_reg_s1/CLK</td>
</tr>
<tr>
<td>5.519</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R29C27[0][A]</td>
<td style=" font-weight:bold;">IO_voltage_reg_s1/Q</td>
</tr>
<tr>
<td>5.522</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td>n83_s2/I0</td>
</tr>
<tr>
<td>5.754</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td style=" background: #97FFFF;">n83_s2/F</td>
</tr>
<tr>
<td>5.754</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td style=" font-weight:bold;">IO_voltage_reg_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td>IO_voltage_reg_s1/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C27[0][A]</td>
<td>IO_voltage_reg_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.754</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[0][A]</td>
<td>count_value_reg_6_s0/CLK</td>
</tr>
<tr>
<td>5.519</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R26C27[0][A]</td>
<td style=" font-weight:bold;">count_value_reg_6_s0/Q</td>
</tr>
<tr>
<td>5.522</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R26C27[0][A]</td>
<td>n24_s/I1</td>
</tr>
<tr>
<td>5.754</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R26C27[0][A]</td>
<td style=" background: #97FFFF;">n24_s/SUM</td>
</tr>
<tr>
<td>5.754</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[0][A]</td>
<td style=" font-weight:bold;">count_value_reg_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[0][A]</td>
<td>count_value_reg_6_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C27[0][A]</td>
<td>count_value_reg_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.754</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>5.519</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/Q</td>
</tr>
<tr>
<td>5.522</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R26C27[1][A]</td>
<td>n22_s/I1</td>
</tr>
<tr>
<td>5.754</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td style=" background: #97FFFF;">n22_s/SUM</td>
</tr>
<tr>
<td>5.754</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_8_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C27[1][A]</td>
<td>count_value_reg_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.754</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_12_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[0][A]</td>
<td>count_value_reg_12_s0/CLK</td>
</tr>
<tr>
<td>5.519</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R26C28[0][A]</td>
<td style=" font-weight:bold;">count_value_reg_12_s0/Q</td>
</tr>
<tr>
<td>5.522</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R26C28[0][A]</td>
<td>n18_s/I1</td>
</tr>
<tr>
<td>5.754</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R26C28[0][A]</td>
<td style=" background: #97FFFF;">n18_s/SUM</td>
</tr>
<tr>
<td>5.754</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C28[0][A]</td>
<td style=" font-weight:bold;">count_value_reg_12_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[0][A]</td>
<td>count_value_reg_12_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C28[0][A]</td>
<td>count_value_reg_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.754</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_14_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[1][A]</td>
<td>count_value_reg_14_s0/CLK</td>
</tr>
<tr>
<td>5.519</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R26C28[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_14_s0/Q</td>
</tr>
<tr>
<td>5.522</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R26C28[1][A]</td>
<td>n16_s/I1</td>
</tr>
<tr>
<td>5.754</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R26C28[1][A]</td>
<td style=" background: #97FFFF;">n16_s/SUM</td>
</tr>
<tr>
<td>5.754</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C28[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_14_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[1][A]</td>
<td>count_value_reg_14_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C28[1][A]</td>
<td>count_value_reg_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.754</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_18_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[0][A]</td>
<td>count_value_reg_18_s0/CLK</td>
</tr>
<tr>
<td>5.519</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R26C29[0][A]</td>
<td style=" font-weight:bold;">count_value_reg_18_s0/Q</td>
</tr>
<tr>
<td>5.522</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R26C29[0][A]</td>
<td>n12_s/I1</td>
</tr>
<tr>
<td>5.754</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R26C29[0][A]</td>
<td style=" background: #97FFFF;">n12_s/SUM</td>
</tr>
<tr>
<td>5.754</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C29[0][A]</td>
<td style=" font-weight:bold;">count_value_reg_18_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[0][A]</td>
<td>count_value_reg_18_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C29[0][A]</td>
<td>count_value_reg_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.754</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_20_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[1][A]</td>
<td>count_value_reg_20_s0/CLK</td>
</tr>
<tr>
<td>5.519</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R26C29[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_20_s0/Q</td>
</tr>
<tr>
<td>5.522</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R26C29[1][A]</td>
<td>n10_s/I1</td>
</tr>
<tr>
<td>5.754</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R26C29[1][A]</td>
<td style=" background: #97FFFF;">n10_s/SUM</td>
</tr>
<tr>
<td>5.754</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C29[1][A]</td>
<td style=" font-weight:bold;">count_value_reg_20_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[1][A]</td>
<td>count_value_reg_20_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C29[1][A]</td>
<td>count_value_reg_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.483</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.812</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[2][A]</td>
<td>count_value_reg_0_s0/CLK</td>
</tr>
<tr>
<td>5.519</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R29C28[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_0_s0/Q</td>
</tr>
<tr>
<td>5.522</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[2][A]</td>
<td>n30_s2/I0</td>
</tr>
<tr>
<td>5.812</td>
<td>0.290</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R29C28[2][A]</td>
<td style=" background: #97FFFF;">n30_s2/F</td>
</tr>
<tr>
<td>5.812</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C28[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C28[2][A]</td>
<td>count_value_reg_0_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C28[2][A]</td>
<td>count_value_reg_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.290, 58.652%; route: 0.002, 0.494%; tC2Q: 0.202, 40.854%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.539</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.867</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[1][B]</td>
<td>count_value_reg_3_s0/CLK</td>
</tr>
<tr>
<td>5.518</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R26C26[1][B]</td>
<td style=" font-weight:bold;">count_value_reg_3_s0/Q</td>
</tr>
<tr>
<td>5.635</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R26C26[1][B]</td>
<td>n27_s/I1</td>
</tr>
<tr>
<td>5.867</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C26[1][B]</td>
<td style=" background: #97FFFF;">n27_s/SUM</td>
</tr>
<tr>
<td>5.867</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C26[1][B]</td>
<td style=" font-weight:bold;">count_value_reg_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[1][B]</td>
<td>count_value_reg_3_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C26[1][B]</td>
<td>count_value_reg_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 42.184%; route: 0.117, 21.269%; tC2Q: 0.201, 36.547%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.539</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.867</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[2][A]</td>
<td>count_value_reg_4_s0/CLK</td>
</tr>
<tr>
<td>5.518</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R26C26[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_4_s0/Q</td>
</tr>
<tr>
<td>5.635</td>
<td>0.117</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R26C26[2][A]</td>
<td>n26_s/I1</td>
</tr>
<tr>
<td>5.867</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C26[2][A]</td>
<td style=" background: #97FFFF;">n26_s/SUM</td>
</tr>
<tr>
<td>5.867</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C26[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[2][A]</td>
<td>count_value_reg_4_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C26[2][A]</td>
<td>count_value_reg_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 42.184%; route: 0.117, 21.269%; tC2Q: 0.201, 36.547%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.542</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.871</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_17_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[2][B]</td>
<td>count_value_reg_17_s0/CLK</td>
</tr>
<tr>
<td>5.518</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C28[2][B]</td>
<td style=" font-weight:bold;">count_value_reg_17_s0/Q</td>
</tr>
<tr>
<td>5.639</td>
<td>0.120</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R26C28[2][B]</td>
<td>n13_s/I1</td>
</tr>
<tr>
<td>5.871</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C28[2][B]</td>
<td style=" background: #97FFFF;">n13_s/SUM</td>
</tr>
<tr>
<td>5.871</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C28[2][B]</td>
<td style=" font-weight:bold;">count_value_reg_17_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[2][B]</td>
<td>count_value_reg_17_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C28[2][B]</td>
<td>count_value_reg_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.934%; route: 0.120, 21.736%; tC2Q: 0.201, 36.331%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.874</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][B]</td>
<td>count_value_reg_9_s0/CLK</td>
</tr>
<tr>
<td>5.518</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[1][B]</td>
<td style=" font-weight:bold;">count_value_reg_9_s0/Q</td>
</tr>
<tr>
<td>5.642</td>
<td>0.124</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R26C27[1][B]</td>
<td>n21_s/I1</td>
</tr>
<tr>
<td>5.874</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C27[1][B]</td>
<td style=" background: #97FFFF;">n21_s/SUM</td>
</tr>
<tr>
<td>5.874</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[1][B]</td>
<td style=" font-weight:bold;">count_value_reg_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[1][B]</td>
<td>count_value_reg_9_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C27[1][B]</td>
<td>count_value_reg_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.874</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[2][A]</td>
<td>count_value_reg_10_s0/CLK</td>
</tr>
<tr>
<td>5.518</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_10_s0/Q</td>
</tr>
<tr>
<td>5.642</td>
<td>0.124</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R26C27[2][A]</td>
<td>n20_s/I1</td>
</tr>
<tr>
<td>5.874</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C27[2][A]</td>
<td style=" background: #97FFFF;">n20_s/SUM</td>
</tr>
<tr>
<td>5.874</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_10_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[2][A]</td>
<td>count_value_reg_10_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C27[2][A]</td>
<td>count_value_reg_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.874</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_11_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[2][B]</td>
<td>count_value_reg_11_s0/CLK</td>
</tr>
<tr>
<td>5.518</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[2][B]</td>
<td style=" font-weight:bold;">count_value_reg_11_s0/Q</td>
</tr>
<tr>
<td>5.642</td>
<td>0.124</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R26C27[2][B]</td>
<td>n19_s/I1</td>
</tr>
<tr>
<td>5.874</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C27[2][B]</td>
<td style=" background: #97FFFF;">n19_s/SUM</td>
</tr>
<tr>
<td>5.874</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[2][B]</td>
<td style=" font-weight:bold;">count_value_reg_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[2][B]</td>
<td>count_value_reg_11_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C27[2][B]</td>
<td>count_value_reg_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.874</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_15_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[1][B]</td>
<td>count_value_reg_15_s0/CLK</td>
</tr>
<tr>
<td>5.518</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C28[1][B]</td>
<td style=" font-weight:bold;">count_value_reg_15_s0/Q</td>
</tr>
<tr>
<td>5.642</td>
<td>0.124</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R26C28[1][B]</td>
<td>n15_s/I1</td>
</tr>
<tr>
<td>5.874</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C28[1][B]</td>
<td style=" background: #97FFFF;">n15_s/SUM</td>
</tr>
<tr>
<td>5.874</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C28[1][B]</td>
<td style=" font-weight:bold;">count_value_reg_15_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[1][B]</td>
<td>count_value_reg_15_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C28[1][B]</td>
<td>count_value_reg_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.874</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_16_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[2][A]</td>
<td>count_value_reg_16_s0/CLK</td>
</tr>
<tr>
<td>5.518</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C28[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_16_s0/Q</td>
</tr>
<tr>
<td>5.642</td>
<td>0.124</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R26C28[2][A]</td>
<td>n14_s/I1</td>
</tr>
<tr>
<td>5.874</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C28[2][A]</td>
<td style=" background: #97FFFF;">n14_s/SUM</td>
</tr>
<tr>
<td>5.874</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C28[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_16_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C28[2][A]</td>
<td>count_value_reg_16_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C28[2][A]</td>
<td>count_value_reg_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.874</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[1][B]</td>
<td>count_value_reg_21_s0/CLK</td>
</tr>
<tr>
<td>5.518</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C29[1][B]</td>
<td style=" font-weight:bold;">count_value_reg_21_s0/Q</td>
</tr>
<tr>
<td>5.642</td>
<td>0.124</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R26C29[1][B]</td>
<td>n9_s/I1</td>
</tr>
<tr>
<td>5.874</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C29[1][B]</td>
<td style=" background: #97FFFF;">n9_s/SUM</td>
</tr>
<tr>
<td>5.874</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C29[1][B]</td>
<td style=" font-weight:bold;">count_value_reg_21_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[1][B]</td>
<td>count_value_reg_21_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C29[1][B]</td>
<td>count_value_reg_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.547</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.876</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[2][B]</td>
<td>count_value_reg_5_s0/CLK</td>
</tr>
<tr>
<td>5.518</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C26[2][B]</td>
<td style=" font-weight:bold;">count_value_reg_5_s0/Q</td>
</tr>
<tr>
<td>5.644</td>
<td>0.125</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R26C26[2][B]</td>
<td>n25_s/I1</td>
</tr>
<tr>
<td>5.876</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C26[2][B]</td>
<td style=" background: #97FFFF;">n25_s/SUM</td>
</tr>
<tr>
<td>5.876</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C26[2][B]</td>
<td style=" font-weight:bold;">count_value_reg_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[2][B]</td>
<td>count_value_reg_5_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C26[2][B]</td>
<td>count_value_reg_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.564%; route: 0.125, 22.426%; tC2Q: 0.201, 36.010%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.547</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.876</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[0][B]</td>
<td>count_value_reg_7_s0/CLK</td>
</tr>
<tr>
<td>5.518</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C27[0][B]</td>
<td style=" font-weight:bold;">count_value_reg_7_s0/Q</td>
</tr>
<tr>
<td>5.644</td>
<td>0.125</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R26C27[0][B]</td>
<td>n23_s/I1</td>
</tr>
<tr>
<td>5.876</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C27[0][B]</td>
<td style=" background: #97FFFF;">n23_s/SUM</td>
</tr>
<tr>
<td>5.876</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[0][B]</td>
<td style=" font-weight:bold;">count_value_reg_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[0][B]</td>
<td>count_value_reg_7_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C27[0][B]</td>
<td>count_value_reg_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.564%; route: 0.125, 22.426%; tC2Q: 0.201, 36.010%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.547</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.876</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_19_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_19_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[0][B]</td>
<td>count_value_reg_19_s0/CLK</td>
</tr>
<tr>
<td>5.518</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R26C29[0][B]</td>
<td style=" font-weight:bold;">count_value_reg_19_s0/Q</td>
</tr>
<tr>
<td>5.644</td>
<td>0.125</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R26C29[0][B]</td>
<td>n11_s/I1</td>
</tr>
<tr>
<td>5.876</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C29[0][B]</td>
<td style=" background: #97FFFF;">n11_s/SUM</td>
</tr>
<tr>
<td>5.876</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C29[0][B]</td>
<td style=" font-weight:bold;">count_value_reg_19_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[0][B]</td>
<td>count_value_reg_19_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C29[0][B]</td>
<td>count_value_reg_19_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.564%; route: 0.125, 22.426%; tC2Q: 0.201, 36.010%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.549</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.877</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_23_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_23_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[2][B]</td>
<td>count_value_reg_23_s0/CLK</td>
</tr>
<tr>
<td>5.518</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R26C29[2][B]</td>
<td style=" font-weight:bold;">count_value_reg_23_s0/Q</td>
</tr>
<tr>
<td>5.645</td>
<td>0.127</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R26C29[2][B]</td>
<td>n7_s/I1</td>
</tr>
<tr>
<td>5.877</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C29[2][B]</td>
<td style=" background: #97FFFF;">n7_s/SUM</td>
</tr>
<tr>
<td>5.877</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C29[2][B]</td>
<td style=" font-weight:bold;">count_value_reg_23_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[2][B]</td>
<td>count_value_reg_23_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C29[2][B]</td>
<td>count_value_reg_23_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.432%; route: 0.127, 22.672%; tC2Q: 0.201, 35.896%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.552</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.881</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_22_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_22_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[2][A]</td>
<td>count_value_reg_22_s0/CLK</td>
</tr>
<tr>
<td>5.518</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R26C29[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_22_s0/Q</td>
</tr>
<tr>
<td>5.649</td>
<td>0.130</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R26C29[2][A]</td>
<td>n8_s/I1</td>
</tr>
<tr>
<td>5.881</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C29[2][A]</td>
<td style=" background: #97FFFF;">n8_s/SUM</td>
</tr>
<tr>
<td>5.881</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C29[2][A]</td>
<td style=" font-weight:bold;">count_value_reg_22_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C29[2][A]</td>
<td>count_value_reg_22_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C29[2][A]</td>
<td>count_value_reg_22_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 41.181%; route: 0.130, 23.141%; tC2Q: 0.201, 35.678%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.556</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.885</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.328</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_value_reg_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_value_reg_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>Clock:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Clock:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[0][B]</td>
<td>count_value_reg_1_s0/CLK</td>
</tr>
<tr>
<td>5.519</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R26C26[0][B]</td>
<td style=" font-weight:bold;">count_value_reg_1_s0/Q</td>
</tr>
<tr>
<td>5.521</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R26C26[0][B]</td>
<td>n29_s/I0</td>
</tr>
<tr>
<td>5.885</td>
<td>0.364</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R26C26[0][B]</td>
<td style=" background: #97FFFF;">n29_s/SUM</td>
</tr>
<tr>
<td>5.885</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C26[0][B]</td>
<td style=" font-weight:bold;">count_value_reg_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>3.126</td>
<td>3.126</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL7[A]</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>5.317</td>
<td>2.191</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[0][B]</td>
<td>count_value_reg_1_s0/CLK</td>
</tr>
<tr>
<td>5.328</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C26[0][B]</td>
<td>count_value_reg_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.364, 64.172%; route: 0.001, 0.215%; tC2Q: 0.202, 35.612%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 3.126, 58.796%; route: 2.191, 41.204%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>0.972</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>1.972</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Clock</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_value_reg_22_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>count_value_reg_22_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>7.140</td>
<td>2.140</td>
<td>tINS</td>
<td>FF</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>9.443</td>
<td>2.303</td>
<td>tNET</td>
<td>FF</td>
<td>count_value_reg_22_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>0.972</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>1.972</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Clock</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_value_reg_21_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>count_value_reg_21_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>7.140</td>
<td>2.140</td>
<td>tINS</td>
<td>FF</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>9.443</td>
<td>2.303</td>
<td>tNET</td>
<td>FF</td>
<td>count_value_reg_21_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>0.972</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>1.972</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Clock</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_value_reg_19_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>count_value_reg_19_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>7.140</td>
<td>2.140</td>
<td>tINS</td>
<td>FF</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>9.443</td>
<td>2.303</td>
<td>tNET</td>
<td>FF</td>
<td>count_value_reg_19_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>0.972</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>1.972</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Clock</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_value_reg_15_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>count_value_reg_15_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>7.140</td>
<td>2.140</td>
<td>tINS</td>
<td>FF</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>9.443</td>
<td>2.303</td>
<td>tNET</td>
<td>FF</td>
<td>count_value_reg_15_s0/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>0.972</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>1.972</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Clock</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_value_reg_7_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>count_value_reg_7_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>7.140</td>
<td>2.140</td>
<td>tINS</td>
<td>FF</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>9.443</td>
<td>2.303</td>
<td>tNET</td>
<td>FF</td>
<td>count_value_reg_7_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>0.972</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>1.972</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Clock</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_value_reg_8_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>7.140</td>
<td>2.140</td>
<td>tINS</td>
<td>FF</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>9.443</td>
<td>2.303</td>
<td>tNET</td>
<td>FF</td>
<td>count_value_reg_8_s0/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>0.972</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>1.972</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Clock</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_value_reg_16_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>count_value_reg_16_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>7.140</td>
<td>2.140</td>
<td>tINS</td>
<td>FF</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>9.443</td>
<td>2.303</td>
<td>tNET</td>
<td>FF</td>
<td>count_value_reg_16_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>0.972</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>1.972</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Clock</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_value_reg_9_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>count_value_reg_9_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>7.140</td>
<td>2.140</td>
<td>tINS</td>
<td>FF</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>9.443</td>
<td>2.303</td>
<td>tNET</td>
<td>FF</td>
<td>count_value_reg_9_s0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>0.972</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>1.972</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Clock</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_value_reg_10_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>count_value_reg_10_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>7.140</td>
<td>2.140</td>
<td>tINS</td>
<td>FF</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>9.443</td>
<td>2.303</td>
<td>tNET</td>
<td>FF</td>
<td>count_value_reg_10_s0/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>0.972</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>1.972</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>Clock</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>IO_voltage_reg_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>4.230</td>
<td>4.230</td>
<td>tINS</td>
<td>RR</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>7.471</td>
<td>3.241</td>
<td>tNET</td>
<td>RR</td>
<td>IO_voltage_reg_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>Clock</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Clock_ibuf/I</td>
</tr>
<tr>
<td>7.140</td>
<td>2.140</td>
<td>tINS</td>
<td>FF</td>
<td>Clock_ibuf/O</td>
</tr>
<tr>
<td>9.443</td>
<td>2.303</td>
<td>tNET</td>
<td>FF</td>
<td>IO_voltage_reg_s1/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>26</td>
<td>Clock_d</td>
<td>6.832</td>
<td>3.468</td>
</tr>
<tr>
<td>25</td>
<td>n55_6</td>
<td>6.832</td>
<td>0.806</td>
</tr>
<tr>
<td>3</td>
<td>count_value_reg[22]</td>
<td>7.419</td>
<td>0.169</td>
</tr>
<tr>
<td>3</td>
<td>count_value_reg[23]</td>
<td>7.387</td>
<td>0.164</td>
</tr>
<tr>
<td>2</td>
<td>IO_voltage_d</td>
<td>9.355</td>
<td>1.846</td>
</tr>
<tr>
<td>2</td>
<td>count_value_reg[0]</td>
<td>7.495</td>
<td>0.658</td>
</tr>
<tr>
<td>2</td>
<td>count_value_reg[19]</td>
<td>7.517</td>
<td>0.174</td>
</tr>
<tr>
<td>2</td>
<td>count_value_reg[20]</td>
<td>7.285</td>
<td>0.156</td>
</tr>
<tr>
<td>2</td>
<td>count_value_reg[21]</td>
<td>7.319</td>
<td>0.161</td>
</tr>
<tr>
<td>2</td>
<td>count_value_reg[18]</td>
<td>7.469</td>
<td>0.156</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R26C28</td>
<td>81.94%</td>
</tr>
<tr>
<td>R26C27</td>
<td>76.39%</td>
</tr>
<tr>
<td>R26C29</td>
<td>76.39%</td>
</tr>
<tr>
<td>R26C26</td>
<td>55.56%</td>
</tr>
<tr>
<td>R29C27</td>
<td>30.56%</td>
</tr>
<tr>
<td>R29C28</td>
<td>13.89%</td>
</tr>
<tr>
<td>R27C28</td>
<td>8.33%</td>
</tr>
<tr>
<td>R27C27</td>
<td>4.17%</td>
</tr>
<tr>
<td>R27C26</td>
<td>2.78%</td>
</tr>
<tr>
<td>R34C28</td>
<td>2.78%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
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